1. Field of the Invention
The invention relates to a method for fabricating a through-silicon via structure, and more particularly, to a method of maintaining the depth of interlayer dielectric layer while fabricating a through-silicon via structure.
2. Description of the Prior Art
The through-silicon via technique is a novel semiconductor technique. The through-silicon via technique mainly servers to solve the problem of electrical interconnection between chips and belongs to a new 3D packing field. The through-silicon via technique produces products that meet the market trends of “light, thin, short and small” through the 3D stacking technique and also provides wafer-level packages utilized in micro electronic mechanic system (MEMS), and photoelectronics and electronic devices.
The through-silicon via technique drills holes in the wafer by etching or laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. The wafer or the dice is then thinned to be stacked or bonded together to form a 3D stack IC. By using this approach, the wire bonding procedure could be omitted. Using etching or laser to form conductive vias not only omits the wire bonding but also shrinks the occupied area on the circuit board and the volume for packing. The inner connection distance of the package created by using the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, is much shorter compared with the conventional stack package of wire bonding type. The performance of the 3D stack IC would therefore be much better in many ways, including faster transmission, and lower noise. The advantage of the shorter inner connection distance of the through-silicon via technique becomes much more pronounced in CPU, flash memory and memory card. As the 3D stack IC could be fabricated to equate the size of the dice, the utilization of through-silicon via technique becomes much more valuable in the portable electronic device industry.
A process for fabricating a through-silicon via structure typically involves following steps. First, at least a metal-oxide semiconductor (MOS) transistor, such as a CMOS transistor is formed on surface of a semiconductor substrate, and contact plugs connecting the MOS transistor are formed thereafter. A through-silicon via electrode having isolating dielectric layer and conductive copper metal is formed by etching through the interlayer dielectric layer and majority of the semiconductor substrate. A plurality of chemical mechanical polishing processes are conducted to form the aforementioned contact plugs and through-silicon via electrode, in which each CMP process is utilized to polish different material layers.
It should be noted that in order to stop a polishing process, such as the aforementioned CMP process, on a particular material layer, a difference in the removal rate under a specific slurry must be provided. As the interlayer dielectric layer and the dielectric layer for isolating through-silicon via are both composed of dielectric material thereby having same removal rate under the same slurry, it would be difficult for a chemical mechanical polishing process to stop on either one of these two layers. Eventually, the depth of the interlayer dielectric layer becomes difficult to control as majority of the interlayer dielectric layer is easily lost during the polishing process.